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109 lines
1.8 KiB
C
109 lines
1.8 KiB
C
#ifndef DSP_REGS_H
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#define DSP_REGS_H
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enum DspReg {
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V0VOLL = 0x00,
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V0VOLR = 0x01,
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V0PITCHL = 0x02,
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V0PITCHH = 0x03,
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V0SRCN = 0x04,
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V0ADSR1 = 0x05,
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V0ADSR2 = 0x06,
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V0GAIN = 0x07,
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V0ENVX = 0x08,
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V0OUTX = 0x09,
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MVOLL = 0x0C,
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EFB = 0x0D,
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FIR0 = 0x0F,
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V1VOLL = 0x10,
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V1VOLR = 0x11,
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V1PL = 0x12,
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V1PH = 0x13,
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V1SRCN = 0x14,
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V1ADSR1 = 0x15,
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V1ADSR2 = 0x16,
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V1GAIN = 0x17,
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V1ENVX = 0x18,
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V1OUTX = 0x19,
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MVOLR = 0x1C,
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FIR1 = 0x1F,
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V2VOLL = 0x20,
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V2VOLR = 0x21,
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V2PL = 0x22,
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V2PH = 0x23,
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V2SRCN = 0x24,
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V2ADSR1 = 0x25,
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V2ADSR2 = 0x26,
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V2GAIN = 0x27,
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V2ENVX = 0x28,
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V2OUTX = 0x29,
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EVOLL = 0x2C,
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PMON = 0x2D,
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FIR2 = 0x2F,
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V3VOLL = 0x30,
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V3VOLR = 0x31,
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V3PL = 0x32,
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V3PH = 0x33,
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V3SRCN = 0x34,
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V3ADSR1 = 0x35,
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V3ADSR2 = 0x36,
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V3GAIN = 0x37,
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V3ENVX = 0x38,
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V3OUTX = 0x39,
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EVOLR = 0x3C,
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NON = 0x3D,
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FIR3 = 0x3F,
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V4VOLL = 0x40,
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V4VOLR = 0x41,
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V4PL = 0x42,
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V4PH = 0x43,
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V4SRCN = 0x44,
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V4ADSR1 = 0x45,
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V4ADSR2 = 0x46,
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V4GAIN = 0x47,
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V4ENVX = 0x48,
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V4OUTX = 0x49,
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KON = 0x4C,
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EON = 0x4D,
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FIR4 = 0x4F,
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V5VOLL = 0x50,
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V5VOLR = 0x51,
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V5PL = 0x52,
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V5PH = 0x53,
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V5SRCN = 0x54,
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V5ADSR1 = 0x55,
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V5ADSR2 = 0x56,
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V5GAIN = 0x57,
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V5ENVX = 0x58,
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V5OUTX = 0x59,
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KOF = 0x5C,
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DIR = 0x5D,
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FIR5 = 0x5F,
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V6VOLL = 0x60,
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V6VOLR = 0x61,
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V6PL = 0x62,
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V6PH = 0x63,
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V6SRCN = 0x64,
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V6ADSR1 = 0x65,
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V6ADSR2 = 0x66,
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V6GAIN = 0x67,
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V6ENVX = 0x68,
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V6OUTX = 0x69,
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FLG = 0x6C,
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ESA = 0x6D,
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FIR6 = 0x6F,
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V7VOLL = 0x70,
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V7VOLR = 0x71,
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V7PL = 0x72,
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V7PH = 0x73,
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V7SRCN = 0x74,
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V7ADSR1 = 0x75,
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V7ADSR2 = 0x76,
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V7GAIN = 0x77,
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V7ENVX = 0x78,
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V7OUTX = 0x79,
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ENDX = 0x7C,
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EDL = 0x7D,
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FIR7 = 0x7F,
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};
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#endif // DSP_REGS_H
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